Early Address Prediction

Achieving low load-to-use latency with energy and storage overheads is critical for performance. Existing techniques either prefetch into the pipeline (via address prediction validation) or provide data reuse in register sharing L0 caches). These a range of tradeoffs between latency, reuse, overhead. In this work, we present prefetching technique that achieves state-of-the-art performance without additional storage, movement, validation by adding tags to file. Our addition file allows us forward (reuse) load from no keep alive beyond instruction’s lifetime increase temporal coalesce requests achieve spatial reuse. Further, show can use existing memory order violation detection hardware validate prefetches forwards design while also forwarding 32% loads (compared 15% sharing), delivering 16% reduction L1 dynamic (1.6% total processor energy), an area overhead less than 0.5%.